One or more embodiments relate to a method of performing a read operation of a nonvolatile memory device and, more particularly, to a method of performing a read operation of a nonvolatile memory device, which is capable of improving reliability of a read operation.
In the read operation of a nonvolatile memory device, data can be read by applying a pre-charge voltage to a bit line electrically coupled to a selected string, applying a read voltage to a word line electrically coupled to a selected memory cell, and sensing a change in the voltage level of the precharged bit line.
FIG. 1 is a sectional view illustrating the problems of a known nonvolatile memory device.
Referring to FIG. 1, the nonvolatile memory device includes a plurality of word lines WL0 to WLn (where n is a natural number) formed on a semiconductor substrate 10. The plurality of word lines WL0 to WLn are formed between a source select line SSL and a drain select line DSL. Each of the plurality of word lines WL0 to WLn, the source select line SSL, and the drain select line DSL has a structure in which a gate insulating layer 12, a floating gate 14, a dielectric layer 16, and a control gate 18 are formed over the semiconductor substrate 10. A contact hole is formed in part of each of the dielectric layers 16 formed in the source select line SSL and the drain select line DSL, thereby electrically coupling the floating gate 14 and the control gate 18. Furthermore, a junction 10a is formed in the semiconductor substrate 10 between the source select line SSL and the plurality of word lines WL0 to WLn, between the plurality of word lines WL0 to WLn, and between the plurality of word lines WL0 to WLn and the drain select line DSL.
A read operation on a memory cell coupled to the third word line WL2 of the word lines is described as an example.
In the read operation of the nonvolatile memory device, as described above, a precharge voltage is applied to a bit line electrically coupled to a memory cell to be read. A pass voltage is applied to the word lines WL1 to WLn electrically coupled to unselected memory cells, and a read voltage is applied to the third word line WL2 electrically coupled to a selected memory cell.
If the selected memory cell is a programmed cell and a read voltage level applied to the selected third word line WL2 is lower than a threshold voltage of the programmed cell, a channel is not formed under the selected memory cell. In this case, before a turn-on voltage is applied to the source select line SSL, a source select transistor electrically coupled to the source select line SSL remains in a turn-off state. Accordingly, a channel is also not formed under the source select transistor. As described above, if both the source select transistor and the selected memory cell are in an off state, a channel boosting phenomenon in which the voltage level rises between the turn-off regions can occur. Referring to FIG. 1, channel boosting can occur in the semiconductor substrate 10 between the source select line SSL and the third word line WL2. However, channel boosting does not occur in the semiconductor substrate 10 toward the drain select line DSL. This is because a turn-on voltage is applied to the drain select line DSL in order to transfer voltage of a bit line BL to an active region.
As described above, if a region where channel boosting occurs and a region where channel boosting does not occur exist in the same string, a high electric field can be formed between the region where channel boosting occurs and the region where channel boosting does not occur, and so hot electrons ‘e’ can be generated. In particular, since the hot electrons ‘e’ are probably infiltrated into memory cells neighboring the selected memory cell toward the source select line SSL, a threshold voltage distribution of memory cells may shift. That is, an unwanted soft program operation can be performed on the memory cell coupled to the second word line WL1 because of the infiltration of hot electrons ‘e’.
If, as described above, the threshold voltage shifts, not only data of the memory cells can be changed, but a width of the threshold voltage distribution of the memory cells can be increased, which may lower reliability of, in particular, a multi-level cell (MLC).